1. Field of the Invention
The present invention relates generally to a logic circuit for fast carry or borrow, more particularly, to a logic circuit for use in an incrementer or decrementer having a transfer gate chain for carry or borrow propagation.
2. Description of the Related Art
FIG. 11 shows a prior art ripple carry type incrementer.
This incrementer asynchronously adds a bit C1 =xe2x80x9c1xe2x80x9d to 4 bit inputs A1 to A4 to obtain 5 bit outputs D1 to D4 and C5. A circuit for each digit is a half adder, and each half adder has the same configuration. A half adder circuit 10 for the least significant digit consists of: an exclusive-OR gate 11 whose output bit D1 takes on xe2x80x981xe2x80x99 when either input bit A1 or C1 is xe2x80x981xe2x80x99 and the other is xe2x80x980xe2x80x99; and an AND gate 12 whose output bit C2 as a carry-out bit to the upper digit takes on xe2x80x981xe2x80x99 when the both input bits A1 and C1 are xe2x80x981xe2x80x99.
Although such a ripple carry type circuit is simple in configuration and can be down-sized on circuit scale, since a carry-in from the lower digit at each digit is logically operated by an AND gate, determination of a carry-out bit C5 is delayed, resulting in a low speed operation. For example, when the input bits A4 to A1 =xe2x80x981111xe2x80x99 is provided in a state C1=xe2x80x981xe2x80x99, carries C2 to C5 sequentially change to xe2x80x981xe2x80x99, and therefore determination of the output value xe2x80x9810000xe2x80x99 is delayed.
FIG. 12 shows a binary carry logic circuit 12A for use in a full adder disclosed in JP 05-61645 A.
This circuit 12A consists of: transfer gates 13 to 15; and inverters 16 to 18. When A1=xe2x80x980xe2x80x99, the transfer gates 13 and 14 are on and off, respectively to be D1=C1. When A1=xe2x80x981xe2x80x99, the transfer gates 13 and 14 are turned off and on, respectively to be D1=*C1, where the symbol * denotes an inverse operator. From these relations, the transfer gates 13 and 14 and the inverters 16 and 17 constitutes an exclusive-OR gate 11A.
When the output bit D1xe2x80x980xe2x80x99, that is, when the input bit A1 and the carry-in bit C1 from the lower digit are both xe2x80x981xe2x80x99, the transfer gate 15 is on to be C2=A1.
According to such a binary carry logic circuit 12A, since the input bit A1 passes through the transfer gate 15 to be the carry-out bit C2 to the upper digit, it seems that the operation is fast. However, the carry-in bit C1, for example, turns on the NMOS transistor of the transfer gate 15 through the inverter 16, the transfer gate 14 and then the inverter 18, which is an obstacle against a high speed operation.
FIG. 13 shows a prior art ripple carry type decrementer.
A half subtractor circuit 10X for the least significant digit is of the same configuration as the half adder circuit 10 with the exception that an inverter 19 is connected between the input bit A1 and one input of the AND gate 12. A borrow B2, which is an output of the AND gate 12, takes on xe2x80x981xe2x80x99 when the input bit A1=xe2x80x980xe2x80x99 and a borrow B1=xe2x80x981xe2x80x99.
Although this decrementer is also of a simple configuration like the incrementer of FIG. 11 to enable a circuit scale to be downsized, since a borrow-in bit from the lower digit at each digit is logically operated in an AND gate, determination of a borrow B5 is delayed, resulting in a low speed operation.
On the other hand, a carry look ahead type incrementer and a carry look ahead type decrementer are faster in operation than those of a ripple carry type. However, the circuit scale thereof is larger.
In such a way, in regard to an incrementer and a decrementer, there is a trade-off relation between a high speed operation and downsizing on circuit scale.
Accordingly, it is an object of the present invention to provide a logic circuit for fast carry or borrow capable of achieving a high speed operation while maintaining an advantage of a ripple carry type with a small circuit scale.
In one aspect of the present invention, there is provided an incrementer comprising a plurality of half adder circuits each adding a carry-in bit to an input bit to generate an output bit and a carry-out bit, the plurality of half adder circuits being connected in cascade in regard to the carry-in and carry-out bits. Each of the half adder circuits other than one for the least significant digit comprises: a transfer gate, having a data input and a data output, turned on when the input bit is active, the data input receiving the carry-in bit; a transistor, having a current channel connected between a power supply potential and the data output, a logic value of the power supply potential being equal to that of the carry-in bit in an inactive state, turned on when the input bit being inactive; and a logic circuit, generating the output bit which is active when either the input bit or the carry-in bit is active; wherein the carry-out bit is on the data output.
With this configuration, since the transfer gates of the half adder circuits other than one for the least significant digit are connected in series to each other and the transfer gates are simultaneously on/off controlled by input bits, a carry bit from the least significant digit can propagate through a transfer gate chain at a high speed in the worst case.
In another aspect of the present invention, there is provided a decrementer comprising a plurality of half subtractor circuits each subtracting a borrow-in bit from an input bit to generate an output bit and a borrow-out bit, the plurality of half subtractor circuits being connected in cascade in regard to the borrow-in and borrow-out bits. Each of the half subtractor circuits other than one for the least significant digit comprising: a transfer gate, having a data input and a data output, turned on when the input bit is inactive, the data input receiving the borrow-in bit; a transistor, having a current channel connected between a power supply potential and the data output, a logic value of the power supply potential being equal to that of the borrow-in bit in an inactive state, turned on when the input bit being active; and a logic circuit, generating the output bit which is active when either the input bit or the borrow- in bit is active; wherein the borrow-out bit is on the data output.
With this configuration, since the transfer gates of the half subtractor circuits other than one for the least significant digit are connected in series to each other and the transfer gates are simultaneously on/off controlled by input bits, a borrow from the least significant digit can propagate through a transfer gate chain at a high speed in the worst case.
Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings.